Dosi Computer Composition Principle Experiment 2: Full Adder Experiment

1.It is mainly composed of 4-bit arithmetic logic operation unit 74LS181, 8-bit data latch 74LS273, 8-group bus transceiver 74LS24 with three-state output, switch, and data display lamp.

2.After the subtraction and one's complement operation, it is implemented with an adder, and the result output is A minus B minus 1, and a forced carry (add 1) is generated at the last bit to get the result of A minus B

3.Cascading mode: parallel, serial.Serial: Connect the carry output pin Cn+4 of the lower 4-bit 74LS181 to the carry input pin Cn of the upper 4-bit 74LS181.When M=0, M has no effect on the carry signal, and the value of Fi is related to the operand Ai, Bi and the low bit to the standard carry Cn+1. When performing arithmetic operations, the operand is represented by complement code; parallel: when M=1Carry out logical operation at the same time, block the carry output Cn+i=0 of each bit, and the operation result Fi of each bit is only related to the operands Ai and Bi.Related to pins M, Cn, Cn+i, Cn.The parallel operation is fast, and the serial needs to wait for the low bit to generate a carry signal.

Register DR1 Register DR2